The present invention generally relates to semiconductor devices and more particularly to a semiconductor integrated circuit device in which a nonvolatile memory device and a logic device are integrated and the fabrication process thereof.
So-called hybrid semiconductor integrated circuit devices are the devices in which logic devices such as a CMOS device and non-volatile semiconductor memory devices such as a flash memory device are integrated on a common substrate. Such hybrid semiconductor integrated circuit devices constitute a product group called CPLD (complex programmable logic device) or FPGA (field programmable gate array), wherein these products form a large market in view of their capability of programming.
On the other hand, there is a large difference in the device structure and also in the operational voltage between flash memory devices and logic devices, and thus, there arises a problem of very complex fabrication process with such hybrid semiconductor integrated circuit devices in which flash memory devices and logic devices are integrated. Because of this, various proposals have been made so far for simplifying the fabrication process of such hybrid semiconductor integrated circuit devices.
For example, Japanese Laid-Open Patent Application No. 2001-196470 bulletin describes a process of fabricating a semiconductor integrated circuit device integrating therein a flash memory device and a logic device according to the process of: forming a well corresponding to the device region of a flash memory device, a well corresponding to the device region of a high voltage transistor, and a well corresponding to the device region of a low voltage transistor; and thereafter forming a floating gate of the flash memory device. However, while this conventional process is straightforward, there are included large number of process steps, and thus, this conventional art suffers from the problem of increased fabrication cost.
On the other hand, Japanese Laid-Open Patent Application No. 11-284152 bulletin describes the technology of: forming wells corresponding to the device regions of the flash memory device and the high-voltage transistor on the substrate; forming the tunneling insulation film, floating gate electrode and the inter-electrode insulation film of ONO (oxide-nitride-oxide) structure; removing the tunneling insulation film, the floating gate electrode and the ONO inter-electrode insulation film from the region of the logic circuit; and thereafter forming a well for the device region of the low voltage transistor in the region from which the tunneling insulation film, the floating gate electrode and the ONO inter-electrode insulation film have been removed, for suppressing the characteristic variation of the low voltage transistor constituting the logic device caused at the time of heat-treatment as much as possible. However, while this prior art can successfully minimize the influence of heat to the low voltage transistor, this technology moves the whole fabrication process of the low voltage transistor to the latter half of the fabrication process of the semiconductor integrated circuit device without clarifying which step of the process steps of the low voltage transistor is sensitive to the heat-treatment, the process has limited degree of freedom, and it is difficult to reduce the number of the process steps.
Further, Japanese Laid-Open Patent Application No. 2002-368145, Japanese Laid-Open Patent Application No. 2001-196470 and Japanese Laid-Open Patent Application No. 10-199994 describe the technology of reducing the number of the process steps while suppressing the characteristic change of the low voltage transistor at the time of the heat-treatment, by using the ion implantation mask provided for the formation of the well of the low voltage transistor also as a mask in the process removing the thick gate insulating film of the high-voltage transistor.
According to this prior art, the influence of the heat at the time of forming the floating gate electrodes of flash memory is prevented from reaching the low voltage transistor, and it becomes possible to realize an operational characteristic comparable to that of ordinary low voltage transistor not integrated with a flash memory for the low voltage transistor. Further, it is possible to reduce the number of the mask steps. However, with this prior art, there arise at least two serious problems as explained below.